Various embodiments of this disclosure relate to data processing and, more particularly, to maintaining command order of address translation cache misses and subsequent hits.
Load and store commands in an input/output (I/O) subsystem target multiple sources and destinations, respectively. A virtual channel number distinguishes these target sources and destinations. All commands that share a virtual channel number are required to maintain a user defined order which may range from relaxed to strict ordering. The ordering policy is not known until after address translation is complete so it is assumed that a strict ordering policy is used through the translation process, which means that all commands must complete in the order that the command is issued within a virtual channel. Commands with different virtual channels can complete in a different order or can pass each other.
Incoming load and store commands signal to the I/O interface a virtual address which corresponds to that I/O subsystem's view of memory. This virtual address needs to be translated into a real address corresponding to the processor's view of the memory map.
Typically an address translation cache is used as part of the translation process to take advantage of the temporal and spatial locality of the I/O command addressing. In a system where the address translation unit uses a cache to hold the translation table entries, a cache miss will affect the command flow due to the added time required for performing a memory fetch and then re-translation of the address of the corresponding command.